Data transmission is an important function in many integrated circuit devices. Efforts are continuously being made to increase the data rate of data transmitted by an integrated circuit. However, it is important to accurately transmit the data at the increased data rate. As bandwidth requirements of wire-line and wireless transceiver systems becomes stringent, a multi-step sampling time-interleaved (TI) analog-to-digital converter (ADC) has become a more desirable solution. Time-interleaved ADCs can achieve wide bandwidth data conversion by interleaving multiple channels that includes sub-ADCs.
However, time interleaved analog-to-digital converters are prone to mismatch between channels. More particularly, mismatch in offset voltage, gain, clock timing skew, and bandwidth between the individual channels may degrade the operation of the TI-ADC. Conventional circuits that compensate for mismatch in the multiple channels require significant hardware. Such circuits are not suitable for high speed operation, such as data transfer rates of 56 gigabits per second (Gb/s). Further, many of the conventional circuits provide foreground calibration, and therefore only provide offline calibration.
Accordingly, circuits and methods that minimize mismatch in offset voltage, gain and timing skew in an analog-to-digital converter are beneficial.